SIMD and Vector Instructions

SIMD (Single Instruction, Multiple Data) lets one instruction perform the same operation on several data elements packed into a single wide register, instead of issuing separate scalar instructions for each element. x86 exposes this through SSE, which added 128-bit XMM0–XMM15 registers holding, for example, four 32-bit floats or two 64-bit doubles, and AVX/AVX2, which extended these to 256-bit YMM registers, and AVX-512, which extended further to 512-bit ZMM registers with eight mask registers (K0–K7) for per-lane predication. The core win is throughput: a single VADDPS on a 256-bit YMM register adds eight 32-bit floats in roughly the same time a single scalar ADDSS adds one, so vectorized code can process array-heavy workloads like image filters or numerical simulations many times faster than scalar loops.

SIMD registers are typeless containers whose interpretation is set by the instruction: MOVAPS/MOVUPS treat 128 bits as four packed single-precision floats, PADDD treats them as four packed 32-bit integers to add, and PSHUFB treats them as sixteen packed bytes for arbitrary byte-lane shuffling. The 'A' in instructions like MOVAPS (Move Aligned Packed Single) means the memory operand must be aligned to the register width — 16 bytes for XMM, 32 for YMM, 64 for ZMM — and using it on unaligned memory raises a #GP general protection fault; MOVUPS (Move Unaligned Packed Single) relaxes that requirement at a historically small performance cost that is largely negligible on modern CPUs with unified load ports. Compilers typically align heap and stack buffers intended for SIMD work using aligned allocation functions or the alignas specifier, and hand-written assembly must do the same when declaring static SIMD buffers, typically via an align directive in the data section.

Mixing legacy 128-bit SSE instructions with VEX-encoded AVX instructions on the same YMM register without a VZEROUPPER in between triggers a costly AVX/SSE transition penalty on many microarchitectures: the CPU must save the full, potentially dirty upper 128 bits of the YMM state before it can safely execute the narrower SSE instruction, because SSE instructions are architecturally defined to leave the upper bits of the corresponding YMM register unmodified, and the hardware has to reconcile that guarantee. The standard fix is to execute VZEROUPPER — which zeroes the upper 128 bits of all YMM registers — at the boundary between AVX-heavy and SSE-heavy code, and this is exactly why compilers automatically insert it at the end of AVX-using functions and why hand-written mixed SSE/AVX assembly must do it explicitly.