Mentor Graphics Calibre

Definition

Calibre is a physical verification software suite, originally developed by Mentor Graphics and now part of Siemens EDA, used to check a finished chip layout against a foundry's manufacturing design rules and to verify that the layout electrically matches its source netlist. It runs design rule checking (DRC) and layout-versus-schematic (LVS) verification as the final quality gate before a chip design is sent to a foundry for fabrication, catching layout errors that would otherwise cause manufacturing defects or non-functional silicon.

Overview

After place-and-route tools like Cadence Innovus or Synopsys IC Compiler generate a physical chip layout, that layout must be checked against thousands of geometric rules specific to the target manufacturing process before a foundry will accept it for fabrication—rules governing minimum wire widths, spacing between shapes, and via placement that ensure the design can actually be printed reliably at that process node. Calibre became the dominant tool for performing this check, known as design rule checking, across the semiconductor industry. Mechanically, Calibre reads a chip layout in a standard format alongside a foundry-supplied rule deck encoding that process's specific manufacturing constraints, then scans the entire layout geometrically to flag any violation of those rules, such as two wires placed too close together or a via that doesn't fully overlap its connecting layer. Alongside DRC, Calibre also performs layout-versus-schematic verification, extracting the actual circuit connectivity implied by the physical layout's shapes and comparing it against the intended netlist to confirm the layout has not introduced shorts, opens, or other connectivity errors during physical implementation. Calibre additionally offers parasitic extraction capability, estimating the resistance and capacitance that real metal wires and vias introduce so later timing analysis can account for effects the earlier synthesis and place-and-route stages could only approximate. Calibre sits at the very end of the digital and analog design flow, after synthesis and place-and-route tools have produced a layout but before that layout is handed off to a foundry for mask generation and fabrication. Because foundries generally require Calibre-clean sign-off specifically—given its position as the industry-standard rule-checking engine most closely aligned with foundry rule decks—it functions less as one option among competing tools and more as a near-mandatory checkpoint for commercial chip tape-outs, even when other tools were used earlier in the flow. In practice, Calibre is used by chip design teams across both digital and analog/mixed-signal design, since analog layouts in particular are drawn more manually and benefit heavily from automated rule checking to catch errors a human reviewer would miss. Design teams working on the most advanced process nodes must also account for increasingly complex rules driven by multi-patterning lithography, which Calibre's rule decks are updated to reflect as foundries release new process nodes. Running Calibre on an advanced process node's full rule deck can take considerable compute time given the sheer number of rules and the size of modern chip layouts, so verification is typically run incrementally on sub-blocks throughout the design process rather than only once at the very end.

Key Features

• Performs design rule checking against foundry-specific manufacturing constraints
• Runs layout-versus-schematic verification to confirm layout connectivity
• Serves as the near-mandatory final sign-off gate before chip tape-out
• Used across both digital and analog/mixed-signal design flows
• Reads foundry-supplied rule decks encoding process-specific geometric rules
• Scales to full-chip layouts on advanced semiconductor process nodes
• Runs incrementally on design sub-blocks throughout the design cycle
• Considered the industry-standard physical verification tool by most foundries

Use Cases

Alternatives

Frequently Asked Questions

Related in Computer Science