CoWoS packaging

Definition

CoWoS (Chip-on-Wafer-on-Substrate) is an advanced semiconductor packaging technology developed by TSMC that stacks multiple silicon dies, such as processor logic and high-bandwidth memory, onto a passive silicon interposer before mounting the assembly onto a substrate. This 2.5D integration approach lets manufacturers combine chips built on different process nodes into a single package with far denser, faster interconnects than traditional side-by-side placement on a circuit board allows.

Overview

As transistor scaling on a single monolithic die became harder and more expensive, chip designers began looking for ways to combine multiple specialized dies—logic, memory, and analog components—into one package rather than shrinking everything onto one piece of silicon. CoWoS was TSMC's answer to that challenge, providing a packaging platform that lets a processor die sit alongside high-bandwidth memory stacks with interconnect density approaching what is possible on-chip, at a point when conventional packaging could no longer keep up with the bandwidth modern processors demanded. The process works in two main steps. First, chip dies are attached and interconnected on top of a silicon interposer, a thin layer of silicon patterned with extremely fine wiring and through-silicon vias that route signals vertically as well as horizontally, which is the "chip-on-wafer" stage. Second, that assembled interposer is itself mounted onto a larger organic substrate for connection to the rest of the system, the "on-substrate" stage, which is where the packaging's name comes from. The interposer's fine-pitch wiring is what allows thousands of high-speed connections between a compute die and adjacent memory dies, far more than a conventional PCB trace layout could support, and this density is what makes it practical to feed a large processor die enough memory bandwidth to keep it busy. CoWoS belongs to a family of advanced packaging techniques sometimes grouped under "2.5D and 3D integration," alongside approaches like fan-out wafer-level packaging and true 3D die stacking with vertical through-silicon vias connecting dies directly to each other. CoWoS is specifically a 2.5D technique: dies sit side by side on the interposer rather than stacked vertically on top of one another, distinguishing it from full 3D stacking approaches, and this choice trades some density for manufacturing yield and thermal management advantages compared to stacking dies directly atop one another. In practice, CoWoS has become closely associated with high-performance AI accelerators and GPUs, where it is used to place compute dies next to high-bandwidth memory stacks to feed data-hungry processors without the throughput bottleneck of off-package memory. The same approach also appears in high-end networking chips and some custom silicon designed for large-scale data center workloads, wherever a single monolithic die cannot economically integrate everything a system needs. Demand for this kind of packaging has grown sharply alongside AI hardware, and packaging capacity itself has become a constraint on how many advanced AI chips can be manufactured, independent of wafer fabrication capacity for the logic die itself. This has made advanced packaging slots, not just leading-edge wafer starts, a strategic bottleneck that chip designers and their customers now plan around well in advance.

Key Concepts

• 2.5D integration places multiple dies side by side on a silicon interposer
• Silicon interposer provides far denser interconnects than PCB-level wiring
• Enables combining chips from different process nodes in one package
• Widely used to pair compute dies with high-bandwidth memory stacks
• Reduces signal distance and latency between logic and memory
• Distinct from full 3D die-stacking approaches with vertical through-silicon vias
• Packaging capacity has become a separate bottleneck from wafer fabrication
• Offered by TSMC as part of its advanced packaging service portfolio

Use Cases

Frequently Asked Questions

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