What is Direct Memory Access (DMA)?
Learn what DMA is, how it offloads bulk transfers from the CPU, and why buffers must be pinned, with an OS interview question walkthrough.
Expected Interview Answer
Direct Memory Access (DMA) is a hardware mechanism that lets a peripheral device transfer data directly to or from main memory without routing every byte through the CPU, freeing the processor to do other work while the transfer happens in the background.
Without DMA, the CPU would have to execute a load-then-store instruction for every single word moved between a device and memory, which wastes cycles on pure data shuffling. With DMA, the CPU instead programs a DMA controller with a source address, destination address, and transfer length, then issues a start command; the DMA controller takes over the memory bus and moves the block itself, only interrupting the CPU once when the whole transfer finishes. Because the DMA controller and CPU can both want the bus at the same time, the controller uses cycle stealing or burst modes to negotiate access, and the OS must ensure buffers involved in DMA transfers are pinned in physical memory so they cannot be paged out mid-transfer. This is the backbone of high-throughput I/O for disks, network cards, and audio hardware, since it removes the CPU as a bottleneck for bulk data movement.
- Frees the CPU from byte-by-byte I/O copying
- Enables high-throughput transfers for disks and NICs
- Overlaps I/O transfer time with useful CPU computation
- Reduces interrupt overhead to one per transfer, not one per word
AI Mentor Explanation
DMA is like a ground manager handing the entire kit-bag delivery job to a dedicated equipment runner instead of personally carrying each item from the pavilion to the boundary one piece at a time. The manager just tells the runner the starting rack, the destination, and how many items to move, then goes back to managing the match while the runner works independently. Only when the whole bag is delivered does the runner tap the manager on the shoulder to confirm completion. This mirrors how a CPU offloads bulk transfers to a DMA controller instead of copying every word itself.
Step-by-Step Explanation
Step 1
Program the controller
The CPU sets up the DMA controller with source address, destination address, and transfer length.
Step 2
CPU released
The CPU issues a start command and continues executing other instructions instead of blocking.
Step 3
Bus-mastered transfer
The DMA controller takes control of the memory bus and moves data directly between the device and memory.
Step 4
Completion interrupt
The controller raises a single interrupt once the entire transfer finishes, notifying the CPU.
What Interviewer Expects
- A clear definition of DMA as CPU-bypassing bulk data transfer
- Understanding of why programmed I/O is expensive without DMA
- Awareness that only one interrupt fires per full transfer
- Knowledge that DMA buffers must be pinned (non-pageable) in memory
Common Mistakes
- Thinking DMA eliminates interrupts entirely rather than reducing them to one per transfer
- Confusing DMA with memory-mapped I/O
- Not knowing that DMA buffers must be pinned so they cannot be paged out mid-transfer
- Assuming DMA and CPU can never contend for the memory bus
Best Answer (HR Friendly)
“Direct Memory Access lets a device move a big chunk of data straight into or out of memory on its own, instead of forcing the processor to shuttle every single byte itself. The CPU just sets up the job and gets on with other work, then gets a single notification once the whole transfer is done, which is what makes disks and network cards fast.”
Code Example
struct dma_descriptor {
unsigned long src_addr;
unsigned long dst_addr;
unsigned long length;
};
void start_dma_transfer(struct dma_descriptor *desc) {
dma_reg_write(DMA_SRC_REG, desc->src_addr);
dma_reg_write(DMA_DST_REG, desc->dst_addr);
dma_reg_write(DMA_LEN_REG, desc->length);
dma_reg_write(DMA_CTRL_REG, DMA_START); /* CPU returns immediately */
}
/* Interrupt handler fires once, when the whole transfer completes */
void dma_interrupt_handler(void) {
dma_reg_write(DMA_CTRL_REG, DMA_CLEAR_IRQ);
wake_up_waiting_process();
}Follow-up Questions
- How does cycle stealing let the CPU and DMA controller share the memory bus?
- Why must DMA buffers be pinned in physical memory?
- What is the difference between DMA and memory-mapped I/O?
- How does scatter-gather DMA handle non-contiguous buffers?
MCQ Practice
1. What is the primary benefit of DMA over programmed I/O?
DMA offloads bulk data movement to a dedicated controller so the CPU is not busy copying each word itself.
2. How many interrupts does a typical DMA transfer generate?
The DMA controller performs the whole transfer autonomously and raises a single interrupt when it finishes.
3. Why must DMA buffers be pinned in physical memory?
The DMA controller operates on physical addresses directly, so the OS must guarantee the buffer stays resident for the duration of the transfer.
Flash Cards
What is DMA? — A mechanism letting devices transfer data directly to/from memory without CPU involvement in each word.
Who moves the data during a DMA transfer? — A dedicated DMA controller, which takes control of the memory bus.
How many interrupts per DMA transfer? — Typically one, raised when the entire block transfer completes.
Why pin DMA buffers? — Because the controller uses physical addresses and the page cannot be evicted mid-transfer.