Intel Quartus

Definition

Intel Quartus Prime is FPGA design and synthesis software used to develop, synthesize, and program logic for Intel (formerly Altera) field-programmable gate array and programmable SoC devices. Engineers use it to convert hardware description language code into a configuration file that programs Intel FPGA hardware, covering the full flow from design entry through simulation, synthesis, place-and-route, timing closure, and device programming.

Overview

Quartus Prime is Intel's design suite for its FPGA product lines, inherited through Intel's acquisition of Altera, and it exists to give engineers a complete path from a hardware description of digital logic to a working configuration loaded onto physical FPGA silicon. Like other FPGA vendor toolchains, it is tied specifically to Intel's own device families, meaning a design intended for Intel FPGAs is developed and implemented within Quartus rather than a vendor-neutral tool. Mechanically, Quartus accepts design descriptions in VHDL, Verilog, or SystemVerilog, or assembled visually through schematic entry, and runs synthesis to translate that description into a technology-mapped netlist targeting the specific logic resources available on the chosen Intel FPGA family. It then performs placement and routing, called the fitter stage in Quartus terminology, mapping logic onto physical lookup tables, registers, and routing resources while satisfying timing constraints, before generating a programming file that configures the device. Quartus includes timing analysis tools to verify that the implemented design meets its required clock frequencies across process, voltage, and temperature variation. Within the FPGA toolchain landscape, Quartus is the direct counterpart to AMD's (formerly Xilinx's) Vivado, and the two are not interchangeable since each targets only its own vendor's silicon; engineers choosing between Intel and AMD FPGA product lines are effectively also choosing between Quartus and Vivado as their development environment. ModelSim, also owned by the Quartus ecosystem's history through Mentor Graphics and now Siemens EDA, has long been a standard simulation companion for verifying Quartus designs before hardware deployment. In practice, Quartus is used across networking equipment, industrial control systems, and increasingly Intel's programmable SoC and structured ASIC-adjacent product lines that combine FPGA fabric with embedded processor cores, similar in concept to AMD's adaptive SoC offerings. Engineers also use Quartus for FPGA prototyping of ASIC designs, letting a design team validate logic behavior in real hardware before committing to a fixed-function chip. As with competing FPGA tools, compile times for large designs on dense chips can be lengthy, and the vendor-specific nature of the tool means portability across FPGA suppliers requires re-implementation rather than a simple recompile. Engineers targeting only smaller or simpler designs, or working across multiple FPGA vendors, sometimes rely more heavily on standard, portable HDL and vendor-neutral simulation to minimize how much vendor-specific tooling knowledge their team needs to maintain. As with Vivado, upgrading to a newer Quartus release can shift place-and-route results even for unchanged source code, so teams managing long-lived designs typically pin a specific tool version for a product's lifetime rather than upgrading continuously.

Key Features

• Support for VHDL, Verilog, and SystemVerilog design entry
• Technology-mapped synthesis targeting specific Intel FPGA families
• Fitter stage performing placement and routing onto FPGA fabric
• Timing analysis across process, voltage, and temperature corners
• Programming file generation for device configuration
• Integration with third-party HDL simulators such as ModelSim
• Support for Intel programmable SoC devices combining FPGA and processor cores
• Design space exploration tools for optimizing timing and resource usage

Use Cases

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Frequently Asked Questions

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