Broadcom Tomahawk
By Broadcom
Broadcom Tomahawk is a family of high-radix Ethernet switch silicon designed for data center spine and leaf networking, providing very high aggregate switching bandwidth in a single chip. It targets hyperscale and large enterprise data…
Definition
Broadcom Tomahawk is a family of high-radix Ethernet switch silicon designed for data center spine and leaf networking, providing very high aggregate switching bandwidth in a single chip. It targets hyperscale and large enterprise data centers that need to move large volumes of traffic between racks of servers with minimal added latency, and it forms the switching core inside many white-box and OEM switches sold for cloud and AI cluster networking.
Overview
A network fabric is only as good as the silicon that moves packets between ports, and in large data centers that silicon has to keep pace with racks full of servers pushing traffic simultaneously. Broadcom Tomahawk is the company's line of merchant switch application-specific integrated circuits built specifically for this problem: high port density, high per-port bandwidth, and low, predictable latency, all on a single chip rather than a multi-chip system. Because it is sold as merchant silicon rather than bundled exclusively into one vendor's box, switch makers across the industry can build systems around the same core chip. Mechanically, a Tomahawk chip is built around a shared packet-buffer switching architecture: incoming frames from many high-speed serdes lanes are classified, looked up against forwarding and access-control tables held in on-chip memory, and scheduled out to egress ports through a shared buffer that absorbs momentary bursts without dropping traffic. Successive Tomahawk generations have increased total switching capacity and per-lane speed while adding deeper buffering and more flexible port breakout options, letting the same silicon serve as either many lower-speed ports or fewer very high-speed ports depending on how a switch vendor configures it. Within Broadcom's own portfolio, Tomahawk sits alongside Jericho, which is built for carrier and service-provider routing with deep buffers and rich features for wide-area traffic engineering rather than raw data center throughput. Tomahawk trades some of that routing sophistication for switching density and cost efficiency, making it the more common choice inside a single data center's spine-leaf fabric. Outside Broadcom, it competes with switch silicon programs from other chip vendors and with fully custom switch ASICs that some hyperscalers design in-house for their own networks. In practice, network engineers encounter Tomahawk indirectly: it is embedded inside switches from multiple hardware vendors and white-box platforms running open network operating systems, so the buying decision is usually about the switch and its software rather than the chip itself. Cloud providers and large enterprises use Tomahawk-based switches to build non-blocking or near-non-blocking Clos fabrics that connect thousands of servers, and the chip's throughput has made it a common building block in networks supporting large-scale AI training clusters, where east-west bandwidth between GPUs is a first-order design constraint. The trade-off is that a merchant switch chip is a fixed-function device: its forwarding pipeline, buffer architecture, and feature set are set by Broadcom's design, so operators who need highly customized packet processing or unusual protocol support may find themselves constrained compared to a fully programmable data plane. Tomahawk's buffer depth, while adequate for most data center traffic patterns, is shallower than Jericho's, which can matter for workloads with long-lived congestion or that need extensive traffic shaping. Organizations building carrier networks or needing deep queuing generally look to Jericho or router-class silicon instead.
Key Features
- High-radix single-chip switching for dense spine-leaf data center fabrics
- Shared on-chip buffer architecture that absorbs traffic bursts across ports
- Configurable port breakout supporting many lower-speed or fewer high-speed ports
- Merchant silicon model sold to multiple switch OEMs and white-box vendors
- High per-lane serdes speeds supporting dense 100G/400G-class port configurations
- Optimized for low, predictable latency rather than deep queuing
- Forwarding and ACL tables implemented in on-chip memory for line-rate lookups
- Widely deployed as the switching core for AI training cluster fabrics