ARM Assembly Cheat Sheet

mov  x0, #5           // x0 = 5mov  x1, x0            // x1 = x0add  x2, x0, x1         // x2 = x0 + x1sub  x3, x2, #1          // x3 = x2 - 1mul  x4, x2, x3            // x4 = x2 * x3udiv x5, x4, x2              // x5 = x4 / x2 (unsigned)and  x6, x0, #0xF               // bitwise ANDorr  x7, x0, x1                  // bitwise OReor  x8, x0, x1                   // bitwise XORlsl  x9, x0, #2                    // logical shift left by 2 (x0 * 4)lsr  x10, x0, #1                    // logical shift right by 1cmp  x0, x1                          // compare (sets NZCV flags)

ldr  x0, [x1]              // x0 = *(int64_t*)x1str  x0, [x1]               // *(int64_t*)x1 = x0ldr  x0, [x1, #8]            // load from x1 + 8 (offset)ldr  x0, [x1, #8]!            // pre-index: x1 += 8, then loadldr  x0, [x1], #8              // post-index: load, then x1 += 8ldp  x0, x1, [sp]               // load pair (common for prologue/epilogue)stp  x0, x1, [sp, #-16]!         // store pair, pre-decrement sp by 16ldrb w0, [x1]                     // load byte, zero-extend into w0ldrsw x0, [x1]                      // load 32-bit signed, sign-extend to x0adr  x0, label                        // PC-relative address of labeladrp x0, label                         // page address (paired with add for full addr)

cmp x0, x1b.eq equal_label      // branch if equalb.lt less_label         // branch if less than (signed)b.ne not_equal_label      // branch if not equalb   loop_start              // unconditional branchbl  my_function                // branch and link: x30 = return addr, jumpret                              // return: jumps to address in x30 (LR)my_function:    stp  x29, x30, [sp, #-16]!    // save frame pointer + link register    mov  x29, sp                    // set up frame pointer    // ... body, x0-x7 hold args, x0 holds return value ...    ldp  x29, x30, [sp], #16          // restore    ret

// NEON vector registers overlay the FP regs: v0-v31, viewed as 8b/16b/4h/8h/2s/4s/1d/2dld1  {v0.4s}, [x0]              // load four 32-bit floats from [x0] into v0ld1  {v1.4s}, [x1]fadd v2.4s, v0.4s, v1.4s          // element-wise add, 4 lanes at oncefmul v3.4s, v0.4s, v1.4s            // element-wise multiplyst1  {v2.4s}, [x2]                    // store the result vector// Multiply-accumulate: v4 += v0 * v1, per lanefmla v4.4s, v0.4s, v1.4s// Horizontal reduce: sum all 4 lanes of v0 into scalar s0faddp v5.4s, v0.4s, v0.4sfaddp s0, v5.2s// Integer SIMD: add 16 bytes at onceadd  v6.16b, v0.16b, v1.16b

// Classic load-linked/store-conditional loop (works on all ARMv8-A)retry:    ldxr    w0, [x1]           // exclusive load    add     w0, w0, #1          // increment    stxr    w2, w0, [x1]         // exclusive store; w2 = 0 on success    cbnz    w2, retry              // retry if another core interfered// LSE atomics (ARMv8.1+) do the same in one instruction, no retry loopldadd   w0, w2, [x1]           // *x1 += w0 (atomic add), old value returned in w2swp     w0, w2, [x1]            // atomic swapcas     w0, w3, [x1]             // compare-and-swap: if [x1]==w0, store w3// Memory barriersdmb ish        // data memory barrier, inner-shareable: order loads/storesdsb sy           // data sync barrier: wait for all memory ops to completeisb                // instruction sync barrier: flush pipeline (e.g. after self-modifying code)

// Conditional select avoids branches entirelycmp   x0, x1csel  x2, x3, x4, gt      // x2 = (x0 > x1) ? x3 : x4cset  x5, eq                // x5 = 1 if last compare was equal, else 0csinc x6, x7, xzr, ne         // x6 = ne ? x7 : (xzr + 1) -- conditional incrementccmp  x0, #0, #4, ne           // conditional compare: only evaluated if previous flag was ne// Bitfield instructionsubfx  x0, x1, #8, #4      // unsigned bitfield extract: bits [11:8] of x1 into x0sbfx  x0, x1, #8, #4        // same but sign-extendedbfi   x0, x1, #4, #8          // bitfield insert: 8 bits of x1 into x0 starting at bit 4bfxil x0, x1, #0, #16           // bitfield extract and insert at the low bits

// Scalar floating point uses s (32-bit) and d (64-bit) registersfmov  s0, #1.0             // load an FP immediatescvtf d1, x0                 // signed int64 -> doublefcvtzs x2, d1                  // double -> signed int64, round toward zerofcvt  s3, d1                     // narrow double -> singlefadd  d0, d1, d2              // d0 = d1 + d2fdiv  s0, s1, s2                // single precision dividefcmp  d0, d1                      // compare, sets NZCVfcsel d2, d0, d1, gt                // conditional select on FP compare resultldr   d0, [x0]                        // load a double from memorystr   s0, [x1, #4]                      // store a float at offset 4