CISC vs RISC Philosophy
x86 is a Complex Instruction Set Computer (CISC) architecture: instructions are variable-length (1 to 15 bytes), can encode a memory operand directly into an arithmetic instruction like add eax, [ebx+4], and a single instruction such as rep movsb can perform an entire memory copy loop. ARM, by contrast, is a Reduced Instruction Set Computer (RISC): instructions are fixed-length (4 bytes in ARM mode, 2 or 4 in Thumb), and only dedicated load/store instructions touch memory — arithmetic instructions like add r0, r1, r2 operate strictly on registers.
Cricket analogy: It's the difference between a bowler like Jasprit Bumrah who can vary pace, seam, and yorker length within one delivery (CISC, one instruction does many things) versus a fielding drill broken into simple fixed steps: collect, pivot, throw (RISC, each step is uniform and separate).
; x86 (Intel syntax): a memory operand is embedded directly in the add
add eax, [ebx + 4]
; ARM (AArch32): load must happen first, arithmetic only touches registers
ldr r2, [r1, #4]
add r0, r0, r2Register Sets and Naming
x86-64 exposes 16 general-purpose 64-bit registers (rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp, r8-r15), several of which carry historical special-purpose roles — rcx for loop counters via loop, rsi/rdi for string instructions. ARM's AArch64 provides 31 general-purpose 64-bit registers (x0-x30), which are far more uniform in purpose, plus a dedicated zero register (xzr) that reads as zero and discards writes, a feature x86 has no equivalent for.
Cricket analogy: x86's specialized registers are like a cricket squad where certain players have fixed traditional roles — a designated nightwatchman or a strict number-3 bat — while ARM's x0-x30 are more like a T20 franchise's flexible batting order where almost anyone can bat anywhere.
Addressing Modes and Instruction Encoding
x86 supports rich addressing modes in a single instruction — base + index*scale + displacement, as in mov eax, [ebx + ecx*4 + 8] — encoded via the ModRM and SIB byte scheme, making instruction lengths highly variable. ARM restricts addressing to simpler load/store forms with optional pre/post-increment, such as ldr r0, [r1], #4 (post-indexed), and every instruction is a fixed 32 bits in ARM mode, which simplifies pipelining and instruction decoding at the cost of needing more instructions overall for equivalent work.
Cricket analogy: x86's ModRM+SIB addressing is like a single delivery that's simultaneously a yorker with reverse swing and a slower-ball variation baked in, while ARM's fixed-width load/store is like a standard length delivery every single ball, predictable in shape but requiring more overs to build pressure.
ARM's Thumb-2 instruction set mixes 16-bit and 32-bit encodings to improve code density, narrowing but not eliminating the size gap with x86's naturally compact variable-length instructions.
Calling Conventions
The x86-64 System V AMD64 ABI (used on Linux/macOS) passes the first six integer arguments in rdi, rsi, rdx, rcx, r8, r9, with the caller cleaning the stack for extra arguments. The AArch64 Procedure Call Standard (AAPCS64) passes the first eight integer arguments in x0-x7, and the return value comes back in x0 for both — but ARM additionally reserves x30 as the dedicated link register (lr) that hardware bl automatically populates with the return address, whereas x86's call pushes the return address onto the stack instead.
Cricket analogy: x86's stack-based return address is like noting the next batter's name on a scorecard sheet that gets consulted later, while ARM's dedicated link register is like the incoming batter already standing at the non-striker's end, instantly ready without checking any list.
Never assume calling conventions are portable across architectures: code that manually manipulates the stack pointer or return address in x86 assembly will not translate to ARM, since ARM relies on the link register rather than a stack-resident return address for simple leaf functions.
- x86 is CISC with variable-length instructions and memory operands embedded in arithmetic; ARM is RISC with fixed-length instructions and separate load/store.
- x86-64 has 16 general-purpose registers with some historically specialized roles; AArch64 has 31 more uniform registers plus a hardware zero register.
- x86 supports complex addressing modes (base+index*scale+displacement) via ModRM/SIB bytes; ARM's addressing is simpler with pre/post-indexing.
- ARM's Thumb-2 mode mixes 16- and 32-bit encodings to improve code density versus pure 32-bit ARM mode.
- System V AMD64 ABI passes the first 6 integer args in rdi/rsi/rdx/rcx/r8/r9; AAPCS64 passes the first 8 in x0-x7.
- ARM uses a dedicated link register (x30/lr) for return addresses; x86 pushes return addresses onto the stack via
call. - Neither architecture's low-level conventions (stack layout, register roles) are portable to the other without full rewriting.
Practice what you learned
1. Which characteristic best distinguishes ARM's RISC design from x86's CISC design?
2. In AArch64, which register serves the role that x86's stack-pushed return address serves in a simple leaf function call?
3. How many integer arguments does the System V AMD64 ABI pass in registers before spilling to the stack?
4. What is the purpose of ARM's xzr register?
5. What technique does ARM's Thumb-2 instruction set use to improve code density compared to standard 32-bit ARM mode?
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