What are DMA Controller Modes?
Learn the three DMA controller modes — burst, cycle stealing, and transparent — with tradeoffs and OS interview questions answered.
Expected Interview Answer
Direct Memory Access (DMA) controller modes describe how a DMA engine shares the memory bus with the CPU while moving data between a device and RAM without the CPU copying every byte itself, and the three classic modes are burst mode, cycle stealing mode, and transparent mode.
In burst mode, the DMA controller takes ownership of the system bus and transfers an entire block of data in one uninterrupted sweep, which is fast but locks the CPU out of memory for that whole duration. In cycle stealing mode, the controller transfers one word, then releases the bus back to the CPU for a cycle before grabbing it again, interleaving DMA transfers with CPU memory access so the CPU is only briefly delayed rather than fully blocked. In transparent mode, the DMA controller only takes the bus during cycles the CPU is not actually using it, such as while the CPU is doing internal ALU work, so the transfer causes no observable slowdown but proceeds very slowly. The choice among the three is a tradeoff between transfer speed and how much the DMA activity is allowed to interfere with normal CPU execution, and the OS or device driver typically configures the controller registers to select a mode appropriate for the device’s throughput needs.
- Offloads bulk data movement from the CPU to dedicated hardware
- Burst mode maximizes transfer speed for large contiguous blocks
- Cycle stealing balances throughput against CPU responsiveness
- Transparent mode hides DMA activity entirely at the cost of speed
AI Mentor Explanation
DMA burst mode is like a groundstaff crew closing the entire outfield to sprint out and relay all the boundary ropes in one uninterrupted dash, finishing fast but stopping play completely while they work. Cycle stealing is like the same crew nipping onto the ground for one rope between deliveries, handing the field back to the players each time, so play is only briefly interrupted rather than halted. Transparent mode is like the crew only stepping on during a drinks break the players were already taking, so nobody notices the work happening at all, just slower.
Step-by-Step Explanation
Step 1
Device requests DMA
A peripheral asserts a DMA request line when it has data ready to transfer to or from memory.
Step 2
Controller requests bus
The DMA controller asserts a bus request to the CPU and waits for a bus grant.
Step 3
Transfer executes per mode
Burst mode moves the whole block at once; cycle stealing interleaves word-by-word with the CPU; transparent mode only uses cycles the CPU was not using.
Step 4
Completion interrupt
The controller signals the CPU with an interrupt once the transfer finishes, so the CPU can process the new data.
What Interviewer Expects
- Correct definitions of burst, cycle stealing, and transparent modes
- Understanding that DMA lets I/O bypass CPU-mediated copying
- Awareness of the speed vs CPU-interference tradeoff between modes
- Mention of the completion interrupt signaling transfer done
Common Mistakes
- Confusing DMA with the CPU itself performing the memory copy
- Thinking burst mode has no downside
- Not knowing cycle stealing interleaves at word granularity
- Forgetting transparent mode trades speed for zero CPU interference
Best Answer (HR Friendly)
“DMA lets a device move data to or from memory without making the CPU copy every byte, and the mode controls how aggressively it grabs the memory bus to do that. Burst mode is fastest but blocks the CPU while it runs, cycle stealing takes turns with the CPU so things stay smooth, and transparent mode only sneaks in during moments the CPU was not using memory anyway, trading speed for zero disruption.”
Code Example
#define DMA_MODE_BURST 0x01
#define DMA_MODE_CYCLE 0x02
#define DMA_MODE_TRANSPARENT 0x03
struct dma_channel {
volatile unsigned *src_addr;
volatile unsigned *dst_addr;
volatile unsigned length;
volatile unsigned mode;
volatile unsigned control;
};
void start_dma_transfer(struct dma_channel *ch, void *src, void *dst,
unsigned len, unsigned mode) {
ch->src_addr = src;
ch->dst_addr = dst;
ch->length = len;
ch->mode = mode; /* burst, cycle stealing, or transparent */
ch->control = 1; /* start bit: controller now owns the bus per-mode */
}Follow-up Questions
- How does the CPU know when a DMA transfer has completed?
- What is the difference between DMA and programmed I/O?
- Why might cycle stealing be preferred for real-time systems over burst mode?
- What role does the memory controller play in arbitrating DMA vs CPU bus access?
MCQ Practice
1. Which DMA mode transfers an entire block without releasing the bus?
Burst mode holds the bus for the full transfer duration, maximizing speed at the cost of blocking the CPU.
2. Cycle stealing mode is characterized by?
Cycle stealing interleaves single-word DMA transfers with CPU bus cycles, minimizing CPU delay.
3. Transparent DMA mode achieves zero CPU interference by?
Transparent mode piggybacks on CPU-idle bus cycles, so it never delays the CPU, at the cost of being the slowest mode.
Flash Cards
What are the three classic DMA controller modes? — Burst mode, cycle stealing mode, and transparent mode.
Which DMA mode is fastest but blocks the CPU most? — Burst mode.
Which DMA mode causes zero observable CPU slowdown? — Transparent mode, since it only uses cycles the CPU was not using.
How does the CPU learn a DMA transfer is done? — The DMA controller raises a completion interrupt.