RISC
RISC (Reduced Instruction Set Computer) is a processor design philosophy that favors a small, simple set of fixed-length instructions, each executing in roughly one clock cycle, in order to simplify hardware and enable faster, more…
Definition
RISC (Reduced Instruction Set Computer) is a processor design philosophy that favors a small, simple set of fixed-length instructions, each executing in roughly one clock cycle, in order to simplify hardware and enable faster, more predictable execution.
Overview
RISC emerged in the late 1970s and 1980s from research at IBM, Berkeley, and Stanford, motivated by the observation that most programs spent the bulk of their time using a small subset of available instructions, while compilers rarely used many of the more complex instructions offered by older designs. RISC architects concluded that a processor could run faster overall by supporting fewer, simpler instructions that each complete quickly, moving complexity out of hardware and into the compiler, which handles combining simple instructions to express more complex operations. RISC designs typically feature a uniform, fixed instruction length, a load-store model where only dedicated load and store instructions can access memory (all other operations work on registers), and a larger set of general-purpose registers than typical CISC designs. These characteristics make RISC instructions well suited to Pipelining (CPU), since predictable instruction size and simpler execution paths let the processor overlap the fetch, decode, and execute stages of many instructions at once, and to Superscalar Architecture designs that dispatch multiple instructions per clock cycle. ARM is the most widely deployed RISC Instruction Set Architecture, powering the overwhelming majority of smartphones and increasingly desktops, laptops, and servers due to its strong performance-per-watt characteristics. RISC-V, a newer, open and royalty-free RISC ISA, has gained significant traction in embedded systems, research, and custom silicon design precisely because its simplicity makes it easier and cheaper to implement than proprietary alternatives.
Key Concepts
- Small, simple, fixed-length instruction set designed for fast execution
- Load-store architecture: only dedicated instructions access memory directly
- Larger general-purpose register sets compared to typical CISC designs
- Well suited to pipelining and superscalar execution due to instruction uniformity
- Shifts complexity from hardware into the compiler, which schedules simple instructions
- Historically associated with strong performance-per-watt efficiency
- Major examples include ARM and the open-standard RISC-V
- Emerged from 1980s research contrasting with growing CISC instruction complexity