What is a Translation Lookaside Buffer (TLB)?
Learn what a TLB is, how it speeds up address translation, TLB hits vs misses, and why huge pages reduce TLB misses.
Expected Interview Answer
A Translation Lookaside Buffer, or TLB, is a small, fast hardware cache inside the CPU that stores recent virtual-to-physical address translations, so the MMU can skip the multi-level page table walk on most memory accesses.
Without a TLB, every memory reference would require the MMU to walk the page table hierarchy in main memory, potentially several sequential memory accesses just to translate one address, which would make every load and store several times slower. The TLB caches a small number of recent virtual-page-to-physical-frame mappings directly in fast on-chip memory, so on a TLB hit the physical address is available in roughly one cycle, and only on a TLB miss does the hardware or OS walk the full page table and insert the new mapping into the TLB. Because the TLB is a cache, it must be kept coherent with the page table: when a page is unmapped, swapped out, or a process context switches to a different address space, the relevant TLB entries must be invalidated (a TLB shootdown on multi-core systems) or the TLB flushed entirely, unless the hardware supports tagged TLB entries with address-space identifiers to avoid full flushes. TLB hit rate is critical to overall performance, which is why techniques like huge pages exist — fewer, larger pages mean a single TLB entry covers more memory, reducing miss rate for large working sets.
- Avoids a multi-level page table walk on most memory accesses
- Delivers near-single-cycle address translation on a hit
- Motivates huge pages to shrink TLB miss rate for large data sets
- Explains why context switches and unmaps require TLB invalidation
AI Mentor Explanation
A TLB is like a scorer keeping a small sticky-note list of the last few batters' exact strike rates memorized, instead of flipping through the full scorebook every single ball. If the batter is on the sticky note, the scorer answers instantly; if not, they must flip through the entire scorebook page by page, which is far slower. Switching to a completely different match means wiping the sticky note clean, since old strike rates no longer apply.
Step-by-Step Explanation
Step 1
Virtual address issued
The CPU generates a virtual address as part of a memory instruction.
Step 2
TLB lookup
The hardware checks the TLB for a cached mapping of that virtual page.
Step 3
Hit path
On a hit, the physical frame number is returned immediately and the access proceeds.
Step 4
Miss path
On a miss, the page table is walked in memory, the translation is inserted into the TLB, and the access retries.
What Interviewer Expects
- A clear definition of the TLB as a hardware cache for translations
- Understanding of TLB hit vs miss cost difference
- Awareness that context switches require TLB invalidation or ASID tagging
- Connection between huge pages and improved TLB hit rate
Common Mistakes
- Confusing the TLB with the page table itself
- Thinking the TLB caches data pages instead of address translations
- Forgetting that a context switch can invalidate TLB entries
- Not knowing why huge pages reduce TLB pressure
Best Answer (HR Friendly)
“A TLB is a small, very fast cache inside the CPU that remembers recent translations from virtual memory addresses to real physical memory locations, so the computer does not have to do a slow multi-step lookup on every single memory access. It matters a lot for performance, because without it every memory access would be several times slower, and it is why techniques like larger memory pages exist to make that cache cover more memory at once.”
Code Example
struct tlb_entry {
unsigned vpn; /* virtual page number */
unsigned pfn; /* physical frame number */
int valid;
};
#define TLB_SIZE 64
struct tlb_entry tlb[TLB_SIZE];
unsigned translate(unsigned vaddr) {
unsigned vpn = vaddr / PAGE_SIZE;
unsigned offset = vaddr % PAGE_SIZE;
for (int i = 0; i < TLB_SIZE; i++) {
if (tlb[i].valid && tlb[i].vpn == vpn) {
return tlb[i].pfn * PAGE_SIZE + offset; /* TLB hit: fast path */
}
}
/* TLB miss: walk the page table, then cache the result */
unsigned pfn = walk_page_table(vpn);
tlb_insert(vpn, pfn);
return pfn * PAGE_SIZE + offset;
}Follow-up Questions
- What happens to the TLB on a context switch?
- How do address-space identifiers (ASIDs) avoid full TLB flushes?
- Why do huge pages reduce TLB miss rate?
- What is a TLB shootdown on a multi-core system?
MCQ Practice
1. What does a TLB primarily cache?
The TLB stores recently used virtual-page-to-physical-frame mappings to avoid repeated page table walks.
2. What happens on a TLB miss?
On a miss, hardware or the OS walks the page table hierarchy to find the mapping, then caches it in the TLB for future accesses.
3. Why do huge pages improve TLB performance?
Since each huge page covers far more memory than a standard page, fewer TLB entries are needed to cover the same working set, cutting misses.
Flash Cards
What is a TLB? — A small, fast hardware cache of recent virtual-to-physical address translations.
What happens on a TLB hit? — The physical address is returned in roughly one cycle, skipping the page table walk.
What happens on a TLB miss? — The page table is walked in memory and the new translation is inserted into the TLB.
Why do context switches affect the TLB? — Stale entries from the old address space must be invalidated or tagged with an ASID.